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Synplicity Enters ASIC Synthesis Market to Address Designer Productivity
SUNNYVALE, Calif.--(BUSINESS WIRE)--June 4, 2001--Recognizing that
productivity is a critical issue facing the electronic design
community, Synplicity Inc. (Nasdaq: SYNP), a leading supplier of
software for the design and verification of semiconductors, today
unveiled its strategy to improve designer productivity within the
application specific integrated circuit (ASIC) synthesis market. A
leading FPGA synthesis and ASIC verification solutions provider,
Synplicity identified several areas in ASIC synthesis where
productivity gains can be made, including runtime, learning curves,
ease of use and engineering resource management. As part of its
comprehensive corporate strategy, Synplicity today disclosed product
plans and partnerships with key EDA, ASIC and library vendors to
support its entry into the ASIC synthesis arena.
In a separate announcement also made today, Synplicity introduced
its first ASIC synthesis product, Synplify ASIC(TM), which leverages
Synplicity's synthesis technology and features runtimes up to 15 times
faster than traditional synthesis products while delivering high
quality of results. The Synplify ASIC product complements Synplicity's
ASIC verification synthesis tools, Certify(TM) and Certify SC(TM). The
Certify product, available for the past two years, has delivered a
high-productivity ASIC verification solution for multi-million gate
ASICs and has been used by more than 70 companies. By working closely
with its Certify customers, Synplicity has sought to validate that the
core synthesis technology can generate high quality of results across
the wide range of coding styles typically used in ASIC synthesis.
``In the ASIC world, synthesis has traditionally been a very
painful process requiring complex scripts and years of experience to
achieve acceptable results,'' said Ken McElvain, co-founder and chief
technical officer of Synplicity. ``The synthesis tools in use today do
not adequately address the productivity needs of engineers, making
synthesis tortuous for the majority of designers. After exploring this
area in detail, we've focused our development efforts on improving
runtimes and easing the learning process for synthesis, and believe we
have developed a product that will deliver a new level of productivity
with high quality of results to this group of designers.''
Rich Wawrzyniak, senior analyst at Semico Research, added,
``Improving designer productivity is an area that has been largely
overlooked by EDA companies. However, with today's skyrocketing design
costs and a shortage of skilled engineers, productivity is an area
that we cannot afford to overlook any longer. With its history of
improving designer productivity in the FPGA synthesis and ASIC
verification realms and its unique approach to synthesis, Synplicity
is well-suited to address this issue in the ASIC synthesis space.''
Proven Technology
Founded in 1994, Synplicity has developed a reputation for
providing fast and easy-to-use FPGA synthesis products that help
enable designer productivity and achieve excellent quality of results.
Synplicity leveraged the unique synthesis algorithms that made its
FPGA products successful -- the Behavior Extracting Synthesis
Technology® (B.E.S.T.(TM)) algorithms -- to develop this new ASIC
synthesis product. This same technology has been proven throughout the
years by the thousands of designers who have used Synplicity's
Certify, Synplify Pro(TM) and Amplify(TM) Physical Optimizer(TM)
products to achieve high performance and quality of results when
compiling multi-million gate ASICs and FPGAs.
Synplicity's vice president of marketing, Andy Haines, said, ``Our
research has shown that more than 30 percent of our existing customers
are developing both ASICs and FPGAs, and many of these customers have
expressed frustration with existing ASIC synthesis products. Customers
have been pressing us to introduce an ASIC synthesis product that
meets their needs. In response to these customers, we have extended
the benefits of our popular Synplify® synthesis technology to ASIC
designers with a fast and easy-to-use product that we expect to
deliver high quality of results.''
Mark Keefer, manager of ASIC design at White Rock Networks, a
next-generation metro optical transport systems provider, added, ``As a
startup in a highly competitive market, the Synplify ASIC product's
focus on productivity without sacrificing results is very attractive
to us.''
Areas for Productivity Gain
Working with its customers and members of its ASIC Synthesis
Advisory Panel, a group of ASIC industry experts, Synplicity
identified several areas where productivity gains can be made within
ASIC synthesis. Areas found to have the most promise for productivity
improvements include:
Runtime -- Defined as the time needed to process a design from one
phase to another through an automated tool, runtime is typically
measured by the amount of the design that can be processed in a
specific period of time such as gates per hour or events simulated per
hour.
Learning curves -- Highly complex tools can require a week to a
month of training time. Even given this timeframe, sufficient
expertise to create a highly optimized and competitive design may take
years to refine. Especially with new tools or methodologies, learning
curve has a large impact on designer productivity.
Ease of use -- Many tools require designers to perform difficult
and manual chores, such as writing scripts, partitioning a design into
more manageable blocks or converting incompatible file formats, before
the tool can perform its own task. Eliminating or reducing the need
for these tedious steps can greatly improve designer productivity.
Engineering resource management -- Considering an individual
designer's experience with a specific tool when assigning tasks can
quickly become a management problem and can lead to a lack of
qualified people able to do specific tasks. An easy to learn and use
tool with fast runtimes can simplify the job of an engineering manager
by increasing the pool of qualified engineers available to perform
synthesis.
Indeed, by leveraging its proven synthesis algorithms and focusing
on improving designer productivity, Synplicity believes it has
delivered a product that is fast and delivers high quality of results.
The product is also easy to learn and use. In fact, Synplicity
believes it is possible for designers to become proficient with the
tool after only one day, especially customers already familiar with
Synplicity's other products.
About Synplicity
Synplicity, Inc. (Nasdaq: SYNP) is a leading provider of software
products that enable the rapid and effective design and verification
of semiconductors used in next-generation networking and
communications hardware and other electronic devices. The company
leverages its innovative logic synthesis, physical synthesis and
verification software solutions to improve performance and shorten
development time for complex programmable logic devices, application
specific integrated circuits (ASICs) and system-on-chip (SoC)
integrated circuits. Synplicity's fast, easy-to-use products offer
extremely high quality of results, support industry-standard design
languages (VHDL and Verilog) and run on popular platforms. As of the
end of March 2001, Synplicity employed over 230 people in its 16
facilities worldwide. Synplicity is headquartered in Sunnyvale, Calif.
Forward-looking Statement
This press release contains forward-looking statements. These
statements relate to future events and involve known and unknown
risks, uncertainties and other factors that may cause Synplicity's
actual product performance or achievements to differ materially from
those expressed or implied by the forward-looking statements. In some
cases, you will be able to identify forward-looking statements by
terminology such as ``anticipates,'' ``intends,'' ``may,'' ``will,''
``expects,'' ``potential,'' ``continue'' or the negative of these terms or
other comparable terminology. Forward-looking statements are only
predictions and the actual events or results may differ materially.
Synplicity cannot provide any assurance that its future results will
meet expectations due to a number of factors, including the continued
growth of demand for FPGAs, ASICs and SoCs, continued acceptance of
Synplicity's existing products and the successful introduction and
widespread market acceptance of Synplicity's new products, especially
Synplify ASIC. For additional information and considerations regarding
the risks faced by Synplicity, see its Registration Statement on Form
S-1 and Form 10-K for the fiscal year ended December 31, 2000, as well
as periodic reports on Form 10-Q as filed with the Securities and
Exchange Commission. Although Synplicity believes that the
expectations reflected in the forward-looking statements are
reasonable, Synplicity cannot guarantee future results, levels of
activity, performance or achievements. In addition, neither Synplicity
nor any other person assumes responsibility for the accuracy and
completeness of these forward-looking statements. Synplicity disclaims
any obligation to update information contained in any forward-looking
statement.
Note to Editors: Synplicity, Behavior Extracting Synthesis
Technology and Synplify are registered trademarks of Synplicity, Inc.
Synplify ASIC, Amplify, Certify, Certify SC, B.E.S.T. and Physical
Optimizer are trademarks of Synplicity. All other brands or products
are the trademarks or registered trademarks of their owners.
Contact:
Synplicity Inc., Sunnyvale
John Gallagher, 408/215-6000 (Reader Contact)
johng@synplicity.com
or
Tsantes/Porter Novelli
Steve Gabriel, 408/369-1500 ext. 27 (Press Contact)
steve@tsantes.com
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